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W9425G6EH
1. GENERAL DESCRIPTION
W9425G6EH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR
SDRAM), organized as 4,194,304 words × 4 banks × 16 bits. W9425G6EH delivers a data bandwidth
of up to 500M words per second (-4). To fully comply with the personal computer industrial standard,
W9425G6EH is sorted into the following speed grades: -4, -5, -5I, -6 and -6I. The -4 is compliant to the
DDR500/CL3 and CL4 specification. The -5/-5I is compliant to the DDR400/CL3 specification (the -5I
grade which is guaranteed to support -40°C ~ 85°C). The -6/-6I is compliant to the DDR333/CL2.5
specification (the -6I grade which is guaranteed to support -40°C ~ 85°C).
All Input reference to the positive edge of CLK (except for DQ, DM and CKE). The timing reference
point for the differential clock is when the CLK and CLK signals cross during a transition. Write and
Read data are synchronized with the both edges of DQS (Data Strobe).
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9425G6EH is ideal for main memory in
high performance applications.
2. FEATURES
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2.5V ± 0.2V Power Supply for DDR333/400
2.6V ± 0.1V Power Supply for DDR500
Up to 250 MHz Clock Frequency
Double Data Rate architecture; two data transfers per clock cycle
Differential clock inputs (CLK and CLK )
DQS is edge-aligned with data for Read; center-aligned with data for Write
CAS Latency: 2, 2.5, 3 and 4
Burst Length: 2, 4 and 8
Auto Refresh and Self Refresh
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = 1
7.8μS refresh interval (8K/64 mS refresh)
Maximum burst refresh cycle: 8
Interface: SSTL_2
Packaged in TSOP II 66-pin, using Lead free materials with RoHS compliant
Publication Release Date:Dec. 03, 2008
-4-
Revision A08
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